Electronic systems typically include circuit boards, and the circuit boards typically include semiconductor devices. Some semiconductor devices communicate with each other using clock signals for timing. For example, devices using a common clock signal can communicate with one another by driving data when sending, and latching data when receiving, using timing derived from the common clock signal.
Clock signals can be used to control timing internal to the semiconductor devices, and can also be used to control timing external to the semiconductor devices. For example, in devices having internal storage elements, or “synchronous” elements, an internal clock signal is “fanned out” to the synchronous elements internal to the device such that the internal synchronous elements can reliably communicate. These semiconductor devices can also drive data from within the device through conductors at the device boundary, and drive signal nodes external to the device.
When a clock signal is received by a semiconductor device, it undergoes a finite amount of delay when entering the device. This delay can be caused by trace impedance, input driver delay, or the like. The clock signal on the semiconductor die is, therefore, delayed with respect to the clock outside the device. When one clock signal has undergone a delay different from another clock signal, the two clock signals are said to have a phase offset. When the clock signal internal to the device has a phase offset relative to a clock signal outside the device, timing from one device to another can be upset, thereby causing errors when the devices are communicating.
Delay lock loops have been devised to add additional clock delay to the clock signal such that the total delay is substantially equal to an integer number of clock periods. If the total delay is an integer number of clock periods, the phase offset is zero. When a device is powered on, or when the device is reset, the delay lock loop begins to operate. Delay lock loops typically add or subtract a unit delay element from the internal clock path each clock period until a desired phase offset between the internal and external clock signals is reached. This can be time consuming, especially if the initial phase offset is large, or if the clock frequency is low.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternate methods and apparatus for controlling phase offsets between clock signals.